1. Field
Exemplary embodiments of the present invention relate to a semiconductor package, and more particularly, to a semiconductor package including multiple chips.
2. Description of the Related Art
Recently, the necessity of semiconductor devices capable of storing a large amount of data or processing a large amount of data in a short time. In addition, semiconductor devices that are capable of performing various functions have gradually increased. Accordingly, semiconductor devices are fabricated according to a method of stacking a plurality of chips performing the same function or different functions in one semiconductor package.
FIG. 1 is a diagram explaining an impedance matching operation in a package including a plurality of chips.
Referring to FIG. 1, an integrated circuit system includes a controller chip 110 and a semiconductor package 120 including a plurality of chips 121 to 124.
The controller chip 110 serves as a controller to control the plurality of chips 121 to 124 provided in the package 120. The plurality of chips 121 to 124 refer to chips, which perform specific operations based on the control of the controller chip 110. For example, the controller chip 110 may include a memory controller, and each of the chips 121 to 124 may include a memory.
Between the controller chip 110 and the package 120, an I/O channel I/O CHANNEL is provided to transmit and receive signals (data). The I/O channel I/O CHANNEL is connected to all of the chips 121 to 124, and each of the chips 121 to 124 exchanges signals with the controller chip 110 through the I/O channel I/O CHANNEL. FIG. 1 illustrates that the I/O channel I/O CHANNEL consists of N lines.
Chip select signals CS0 to CS3 are allocated to the plurality of chips 121 to 124 in the package 120, respectively. Each of the chip select signals CS0 to CS3 decides which chip is to exchange signals with the controller chip 110 among the plurality of chips 121 and 124. For example, while the chip select signal CS2 is activated, the chip 123 transmits and receives signals through the I/O channel I/O CHANNEL based on the control of the controller chip 110.
The respective chips 121 and 124 store their impedance settings therein, and include termination circuits 141 to 144 provided therein, respectively. The termination circuits 141 to 144 are configured to terminate the I/O channel I/O CHANNEL to the stored impedance settings to have an impedance matching. The termination operations of the termination circuits 141 to 144 are performed when the termination signals ODT0 to ODT3 allocated to the respective chips 121 to 124 are activated. The plurality of chips 121 to 124 may have different impedance settings, and the termination operations of the respective chips 121 to 124 may be performed at the same time. For example, the impedance setting of the chip 121 may be set to 60Ω, and the impedance setting of the chip 122 may be set to 120Ω. When the termination signal ODT0 is activated, the termination circuit 141 of the chip 121 terminates the I/O channel I/O CHANNEL to 60Ω, and when the termination signal ODT1 is activated, the termination circuit 142 of the chip 122 terminates the I/O channel I/O CHANNEL to 120Ω. Furthermore, when the termination signal ODT0 and the termination signal ODT1 are activated at the same time, the termination circuits 141 and 142 of the chips 121 and 122 terminate the I/O channel I/O CHANNEL at the same time. Therefore, the I/O channel I/O CHANNEL is terminated to 40Ω, which is a parallel impedance value of 60Ω and 120Ω.
That is, when the I/O channel I/O CHANNEL is connected to the respective chips 121 to 124 in the package 120 and the termination circuits 141 to 144 are provided in the respective chips 121 to 124 as illustrated in FIG. 1, the controller chip 110 may set different impedance values for the respective chips 121 to 124, and the number of chips whose termination operations are enabled may be controlled by selecting chips whose termination operations are enabled among the plurality of chips. Accordingly, it is possible to freely control the impedance value to which the I/O channel I/O CHANNEL is terminated.